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Completed Projects

Sr.No.

Name of the Scheme

Title of the project

Funding Agency

Duration

Amount Sanctioned

01.

Major Research Project

An innovative interfacial control layer on Ge channel substrate for the effective fabrication and integration of novel "Ge/ALD High-k/capping layer/ Metal (bilayer) Gate stacks" for future Nano electronics applications.

DST Nano-mission, New Delhi

3 Yrs. (1st Nov 2012-30th March 2016)

50.66 lacs

02.

Major Research Project

Deposition and characterization of silica aerogel low-k thin films as interlayer dielectric (ILD) in ULSI circuits

SERB, DST, New Delhi

3 Yrs. (1st Oct. 2012-30th Sep. 2015)

22.34 lacs

 03.

 Research Project

 Surface modification and Electrical characterization of Low-K thin film for Interlayer dielectric application in Nanoelectronics

 CSIR, New Delhi

 3 Yrs. (1st Feb. 2009-31st Jan. 2012)

 15.5 lacs

 04.

 Major Research Project

 Investigation, fabrication and characterization of different MIS structures for ULSI technology

 UGC 

 2 Yrs. (1st May. 2009-30th April. 2011)

 12.24 lacs

05.

Major Research Project

Characterization of Dielectric films deposited by PECVD system

UGC

3 Yrs. (1st Jan. 2005-31st Dec. 2007)

10.67 lacs

 06.

 Center of Excellence in Nanoelectronics (CEN) under Indian Nanoelectronics User Program (INUP)

 Characterization of Ge/SiC high-k deposited thin films for advanced CMOS technology

 CEN, IIT Mumbai

 12 Weeks

 Collaborative work under INUP

 07.

 Center of Excellence in Nanoelectronics (CEN) under Indian Nanoelectronics User Program (INUP)

 Fabrication and characterization of Ge/ Oxide/Metal gate stacks

 CEN, IIT Mumbai

 1 Year

 Collaborative work under INUP

 08.

 Center of Excellence in Nanoelectronics (CEN) under Indian Nanoelectronics User Program (INUP)

 Fabrication and characterization of novel metal gate High-k based MOS capacitors for future ULSI technology

 CEN,IIT Mumbai

 2yrs (2009-2011)

 Collaborative work under INUP

 09.

 Center of Excellence in Nanoelectronics (CEN) under Indian Nanoelectronics User Program (INUP)

 Fabrication and characterization of novel "Ge/high-k/capping layer/Metal (bilayer) Gate stacks" for advanced CMOS technology.

 CEN,IIT Mumbai

 1yrs (2012-2013)

 Collaborative work under INUP

 10.

 Center of Excellence in Nanoelectronics (CEN) under Indian Nanoelectronics User Program (INUP)

 Characterization of surface modified low-k thin films for ILD applications in nanoelectronics

 CEN,IIT Mumbai  

 3Months 

 Collaborative work under INUP

 11.

 Ion irradiation beam time

 Investigation of radiation effect on low dielectric thin films for CMOS/VLSI technology

 IUAC, New Delhi

 1 run-4 shift (32 hours)

 Collaborative work under BTR-1 scheme, IUAC;

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