Current Research Students

Sr.No. Name & Photo Details
1

Mr. Anil S. Gaikwad

MSc (Energy Studies, Physics) 2010
Currently working as UGC-BSR Fellow, UGC, New Delhi
Ph.D. Topic: "Synthesis and Characterization of Silica Aerogel Thin Films As Inter Layer Dielectrics (ILD) In ULSI Circuits."
Year of registration: May 2013
E-mail: asgaikwad@nmu.ac.in, asgaikawad@gmail.com

2

Mr. Vilas S. Patil


MSc (Electronics) 2012
Currently working as UGC-BSR Fellow, UGC, New Delhi
Ph.D. Topic: "Structural and electrical characterization of Atomic Layer Deposition (ALD)System deposited High-k films based MOS devices for advanced CMOS technology."
Year of registration: May 2013
E-mail: vilasp731@gmail.com

3

Ms.Khushabu S. Agrawal

MSc (Electronics) 2012
Department of Science and Technology (DST) , New Delhi Inspire Fellow
Ph.D. Topic: "Deposition of rare earth oxides by ALD and its applications for alternative gate stack devision"
Year of registration: Aug. 2013
E-mail: khushisagrawal2191@gmail.com

4

Ms. Viral N. Barhate

MSc (Electronics) 2012
Ph.D. Topic: " Deposition of high-k dielectrics ultra thin films by using PEALD on compound semiconductors."
Year of registration: Feb. 2015
E-mail: viral.barhate@gmail.com

6

Miss. Swati Gupta

M.Sc. Physics (2012)
Currently working as project assistant on SERB, DST funded research project entitled : Deposition and characterization of silica aerogel low k thin films as interlayer dielectric (ILD) in ULSI circuits.
E-mail: gswati030@gmail.com

11

Miss. Namrata Pawar

M.Sc.(Inorganic Chem.)and M.Tech.(Oil and Surfactant Technology)
Currently working as project assistant on SERB, DST funded research project entitled : Deposition and characterization of silica aerogel low k thin films as interlayer dielectric (ILD) in ULSI circuits
E-mail: nmu.2510@gmail.com

12

Mr. Rahul Salunke

M.Sc.(Electronics) 2013
Currently working as project assistant on Nano Mission, DST funded research project entitled " An innovative interfacial control layer on Ge channel substrate for the effectiveFabrication and integration of novel "Ge/ALD High-k/capping layer/ Metal (bilayer) Gate stacks" for future nanoelectronics applications".
E-mail: rippusalunke@gmail.com


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